1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a Dynamic Random Access Memory (DRAM) capable of performing a mask write operation.
2. Description of Related Art
In a DRAM including a plurality of input and output terminals (hereinafter referred to as I/O terminals), writing may not be always performed for all the I/O terminals. In such a case, mask signals are input to the I/O terminals where the writing is not performed. In a cell array including a cell which corresponds to the I/O terminal receiving the mask signal, a main I/O pair may be precharged instead of writing. A precharge operation of the main I/O pair is controlled by a control circuit.
FIG. 7 is a circuit diagram of a related control circuit. In the control circuit, a mask On/Off signal, which is an internal signal of the control circuit, is generated according to a mask signal received from an outside of the control circuit. An address signal /ADV is input to one input terminal of an NAND circuit 82 through a buffer 81. A clock CLK is input to the other input terminal of the NAND circuit 82 through buffers 98 and 99. The signal output from the NAND circuit 82 is input to a register 84. A write enable signal /WE which is input from the outside is input to the register 84 through a buffer 85. In other words, the register 84 synchronizes the write enable signal /WE with the address signal /ADV to output the synchronized signal to a pulse generator 86. The pulse generator 86 sets a pulse width of the generated pulse signal in accordance with the output of the register 84. The pulse generator 86 outputs this signal which will be output later as a write amplifier enable 2 signal. The signal output from the pulse generator 86 is input to one input terminal of an NAND circuit 88 through a mask determination waiting delay circuit 87.
The mask signal input from the outside is input to a register 93 through buffers 91 and 92. The register 93 synchronizes the mask signal with the clock CLK received through the buffers 98 and 99, and outputs the synchronized mask signal. The signal output from the register 93 is output to the other input terminal of the NAND circuit 88 through buffers 94, 95, and 96. The signal as the write amplifier enable 2 signal is output from the NAND circuit 88 through a buffer 89. The write amplifier enable 2 is a control signal for a write amplifier to be active.
The signal output from the register 84 is input to one input terminal of the NAND circuit 97, and the signal output from the register 93 is input to the other input terminal of the NAND circuit 97 through the buffers 94 and 95. The output of the NAND circuit 97 is output as a mask On/Off signal in the chip. The precharge signal generated in the chip is output to a pulse generator 100. The pulse generator 100 generates a pulse signal (control signal Pre) in accordance with the signal level of the precharge signal, and outputs this pulse signal to one input terminal of an NAND circuit 102 through a mask determination waiting delay circuit 101. The mask On/Off signal is input to the other input terminal of an NAND circuit 102. The signal output from the NAND circuit 102 is input to one input terminal of an NAND circuit 103. A chip select signal /CS is input to the other input terminal of the NAND circuit 103 through a delay element group 104 and a buffer 105. The output of the NAND circuit 103 is an MIO precharge signal controlling precharge of the main I/O.
FIG. 8 is a timing chart of each control signal in a related DRAM. In FIG. 8, one cycle (from A′ to C) indicates a writing cycle for each one bit. The mask signal input from the outside is input (updated) for each one cycle. In FIG. 8, the writing operation is performed in periods I, II, and III, and the mask operation is performed in a period IV. In the related DRAM, the mask On/Off signal is monitored before the precharge operation, as shown in the period A′ of the cycle 4. The control circuit determines whether the precharge operation is to be started in accordance with a signal level (H/L) of the monitored mask On/Off signal.
Such a DRAM is also disclosed in Japanese Unexamined Patent Application Publication No. 2001-202782. In Japanese Unexamined Patent Application Publication No. 2001-202782, the semiconductor device comprises a write mask circuit, and the write mask circuit sets a write mask signal /WM (corresponding to the mask On/Off signal) which is asynchronous with an internal clock. A write driver receives the output of the write mask circuit, and precharges a pair of write data lines (paragraph 0036).
FIG. 9 is a timing chart showing a precharge operation of the main I/O of the DRAM disclosed in Japanese Unexamined Patent Application Publication No. 2001-202782. In FIG. 9, GLOW and /GLOW correspond to the main I/O pair. In the DRAM disclosed in Japanese Unexamined Patent Application Publication No. 2001-202782, the main I/O pair is separated into a common signal line GLOW for a write operation, and a common signal line pair GLOR for a read operation. In the periods from t1 to t1−1, from t2 to t2−1, and from t3 to t3−1, the write enable signal /WE is activated. After the write enable /WE is activated, the precharge control circuit outputs the write mask signal /WM to the GIO line write driver.
Such a DRAM is also disclosed in Japanese Unexamined Patent Application Publication Nos. 2000-132964 and 2003-196985, for example.
However, in the related DRAM, it is determined whether the precharge operation is to be started in accordance with the determination result of monitoring the signal level of the mask signal input from the outside. Accordingly, the control signal needs to be input to the cell after the determination of the mask signal. In summary, in the related DRAM, the control signal needs to be delayed, which prevents high-speed operation.
In recent years, in a memory product such as a mobile SDRAM and a macro product where the mobile SDRAM is mounted, large capacity, high-speed operation, and low power consumption (low stand-by current) are strongly demanded. A refresh operation performed in the cell accounts for a large percentage of the stand-by current.
A period of the refresh operation needs to be set as long as possible in order to make the stand-by current lower. A restore level of the cell needs to be maximized in order to make the period of the refresh operation longer. However, when the start of the precharge operation delays such as in the related DRAM, it is impossible to secure enough time for the restore operation, which is performed after the precharge operation. Therefore, it is impossible to store enough charges in the cell, and the refresh period needs to be set short. On the other hand, when the restore level of the cell is set maximum, it is needed to secure enough time for the restore operation of the cell. Hence, the high-speed operation cannot be obtained. In summary, there is a trade-off relationship between the low stand-by current and the high operation speed. Accordingly, in the related DRAM, it is difficult to realize both high speed operation and the low stand-by current because of delaying of the start of the precharge operation.